01-14-2019 07:23 PM
Please find the below comment per your two questions.
1. The MDC, MDIO pins are 3.3V tolerant.
2. I believe you are refer to our application note "CAP-AN102-R" for the backplane design. Please follow the [Backplane Connection/Termination] Figure you attached and follow the [Table1: Termination Bias Requirements] Device BCM53262/M/S.
02-25-2019 06:07 AM
Thanks for the above reply. A few more queries:
1. According to the datasheet, the pins XTALI and XTALO are not 3.3 V tolerant. Are other pins in this device 3.3 V tolerant?
2. Can SPI and reset coming from CFPGA(3.33V) compatible to the BCM device pins? If not, how should they be connected?
03-04-2019 07:31 PM
Please find the comment below per your questions:
1. Right, the pin XTALI and XTALO are 2.5V level and not 3.3V tolerant.
The 3.3V tolerant pins are including the configuration pins, programming interface pins, MDC/MDIO pins, LED pins and Reset pin.
2. It's fine the SPI pins are coming from your CFPGA device, suggest please follow the SPI driver in our SDK SW to implement.
For reset pin, highly recommend to use the external reset device to provide the reset siganl to BCM53286. And please make sure to
refer to our design guide application note 5328X-AN103-R "Core and I/O Power Sequencing Requirement" section to tollow our
power on sequencing requirement.