With meltdown and the associated impacts to performance, I've read a lot that a processor capable of PCID is able to mitigate this impact in some scenarios. This capability appears to have been made available with Westmere processors.
My hosts in my lab have X5675s in them, which are west mere processors. I have verified the presecense of this flag by booting the host to a gentoo live CD and executing /proc/cpuinfo (screenshot).
I have my cluster configure to run *without* EVC, and when I run /proc/cpuinfo on both an ubuntu VM and a Centos 7 VM - I *do not* see the PCID flag; however at work when I check on VMs running the same CentOS Kernel version, same ESXi version, but on E5-2680 v4s - I see the pcid flag.
What is ESX doing to hide these flags from the guest on my westmere chips, but then exposing them on a newer chip?
Lab VM:
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 44
model name : Intel(R) Xeon(R) CPU X5675 @ 3.07GHz
stepping : 2
microcode : 0x15
cpu MHz : 3066.775
cache size : 12288 KB
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 11
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts mmx fxsr sse sse2 ss syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts nopl xtopology tsc_reliable nonstop_tsc pni pclmulqdq ssse3 cx16 sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer aes hypervisor lahf_lm tsc_adjust arat
bogomips : 6133.55
clflush size : 64
cache_alignment : 64
address sizes : 42 bits physical, 48 bits virtual
power management: