I am unaware of any such documentation.
In addition to the PMCs, many MSRs are not virtualized. (Unsupported MSRs read as zero and sink all writes.) BTS and PEBS are also not virtualized.
Where there are CPUID feature bits available to indicate the presence or absence of a feature, the bits for a non-virtualized feature are masked out under binary translation and under hardware virtualization. Direct execution of CPL3 code does not provide the ability to perform such masking. Features that are masked out include most power management features, MONITOR/MWAIT, x2APIC, hyper-threading, 1GB superpages, VT-x and AMD-V.