06-11-2018 07:17 AM
I am trying to establish a SGMII connection on the WAN Port 5 (from a Zynq via MAC) and a RGMII connection (to a Phy-Port).
I want to configure the BCM53134P over SPI.
What I red so far in the data sheets and programming guides, are the following necessary register:
|Id||Name||Address (SPI Page: SPI Offset)||Value (hex)||Description|
|1||WAN Ports selection||0x00 : 0x26||0x0020||Which Ports are WAN ports|
|2||IMP Port traffic register||0x00 : 0x08||0x1C||IMP port Control register|
|3||IMP Port State Override register||0x00 : 0x0E||0x8A||1Gbps and Full Duplex|
|4||STS_Override Port 5 (WAN)||0x00 : 0x5D||0x4B||1Gbps, Full Duplex and Uplink|
Since I am using port 5 as a regular WAN port, I don't need to set the Reg(0x02 : 0x00) bit: Correct?
Do I miss something?
Thank for your help!
thanks for your help. However, I could not establish the connection, yet. I sorted some questions, which would help me a lot if you could
1. After setting the speed to 1000Mb/s as described above, the SGMII ist still not working. Has the SGMII Port auto-negotiation ability? If yes, is it possible to disable it?
2. Can you upload the missing register sheets (e.g. page 0x14, page 0xe6)?
3. 53134-AN103-R(1).pdf says: "Packets received from a WAN port are forwarded only to the CPU through the IMP port". Is it the same as for SGMII? Is communication even possible without IMP port for the SGMII?
4. Has WAN_VOL_SEL any influence on BCM53134P, since port 5 is used as SGMII port?
5. Why are there two strapping pins for WAN/SGMII selection: WAN mode decides if SGMII is on port 8 or not, SGMII_P8_SEL does basically the same?
6. I want to establish data on port 8 and SGMII on port5: Therefore, there is no WAN-port necessary, correct?
7. 53134-AN103-R(1).pdf and 53134P-DS101-R(1).pdf says strapping pin LED6 is IMP MODE. However, later it is stated that LED06 is the SGMII_P8_SEL pin. Can you please clarify, what is the truth and update the sheets?
8. What is the background of the SGMII_TESTN / -P signal?
9. Are the register for page 0x14 for the port 5 (since PhyAddress = 4)?
Thanks a lot in advance!
Message was edited by: Clark Gable
06-17-2018 09:39 PM
Right, you do not need to set the Reg(0x02: 0x00).
For 53134P Port5 SGMII configure,
- besides to ensure follow datasheet strap pin setting and using 50MHz crystal clock for SGMII interface, please follow below SGMII registers configure.
This article describes how to configure the BCM53134 B0/B1 chip’s SGMII port speed through the SPI or MDC/MDIO interface. It requires register writes to configure the BCM53134 B0/B1’s SGMII port speed on the:
There is an SGMII Status Register (0xe6: 0x40) to check the SGMII's interface speed configuration status.
09-05-2018 02:51 AM
Hi @ryanl : Thanks for your help.
Actually, there were several things to establish the SGMII connection in my case, which I'd like to document :
I hope, you will add these things into the data sheets / documentation!
04-16-2019 07:19 PM
Thanks for the asking.
We put the configure registers setting sequence in KB article as attached, not in Register Programming Guide doc.
Customers just need to follow up the registers programming sequence.
And the registers are for our internal SerDes phy design, the registers descriptions information not be disclosed for customers.