CA Datacom CADRE

Introduction CA Datacom® and the IBM z Integrated Information Processor (zIIP)

By Sheila Miller posted 10-01-2020 02:03 PM

  

By Kevin Shuma – October 1, 2020

 

Over the last few months, we received several inquiries asking for updated information about the utilization of zIIP processors within the CA Datacom® environment. This post provides a brief history of zIIP processing in CA Datacom and updated information for the current CA Datacom Version 15.1 delivery.


IBM introduced the zIIP
(system Z Integrated Information Processor) in 2006. IBM hardware purchase costs for the zIIP processors are significantly lower than the corresponding charges for GP (General Purpose) processors. More importantly to the customer, zIIP processors are not included in the billable processing power, which is the basis for many software license fees. Mainframe customers can see major savings by shifting a portion of their mainframe computing workload from GP processors to zIIP processors.


The software must follow a specific set of rules set by IBM to utilize the zIIP processors. One of the key rules is the workload that is dispatched on a zIIP processor must be executed on a WLM SRB (Workload Manager Service Request Block). 


Additional rules include limitation of what types of processing are eligible to execute on a zIIP processor. For example, physical I/O (EXCP) processing is not eligible. To utilize zIIP processors, the executing program must be able to split its workload between operations that are executable on a zIIP and those that must execute on a general purpose (GP) processor. 


When zIIP processors were initially delivered by IBM, CA Datacom® utilized TCBs (Task Control Blocks) to execute the majority of its workload. Therefore, CA Datacom Version 11.0 (and earlier) could not exploit zIIP processors.  


CA Datacom exploitation of zIIP processors
began with the delivery of CA Datacom/DB for zOS Version 12.0 (May 2009). With Version 12.0, CA Datacom customers had the ability to exploit the IBM zIIP processors by offloading a portion of the CA Datacom Multi-User (MUF) address space workload to available zIIP processors. The CA Datacom MUF is the persistent address space that handles the majority of database requests for the CA Datacom user. By offloading part of the database request workload to zIIP processors, CA Datacom customers were able to improve the overall throughput of the MUF address space while reducing GP CPU consumption.


To exploit zIIP processing in CA Datacom, the MUF address space must be enabled using the Symmetrical Multi-Processing option (SMPTASK n,n,n,SRB) which enables the use of multiple processing TCBs to process the database request workload. Specifying SRB indicates that the WLM enabled SRBs are enabled to help with the database request workload. 


In the current implementation, SRB/TCB pairs are used to process the database request workload with eligible work processed on the WLM SRB (zIIP eligible). Non-eligible work is processed on the TCB (GP CPU). 


Note: If no zIIP processors
are available in the system, or the zIIP processors are overloaded, the WLM SRB workload is re-directed to the GP processors for processing. This ensures that the workload completes as fast as possible on whatever processors are available.


With each CA Datacom delivery, zIIP offload improvements have been implemented
to increase the percent of the database request workload that is eligible to run on the WLM SRBs of the MUF therefore increasing the zIIP offload capabilities.


For most sites, a ratio or percentage between zIIP CPU seconds consumed and GP CPU seconds consumed by the MUF address space is a simple way to represent the amount of zIIP offload that is occurring:

zIIP offload % = zIIP CPU seconds / (zIIP CPU seconds plus GP CPU seconds)

Using the above calculation, we estimate that the typical CA Datacom z/OS site with zIIP processors available can see MUF address space offloads of:

Release 12.0 – zIIP offload percentages 20-30%
Release 14.0 – zIIP offload percentages 40-50%
Release 14.2 – zIIP offload percentages 70-85%
Release 15.0 - zIIP offload percentages 75-90%
Release 15.1 – zIIP offload percentages 75-95%


As a rule of thumb,
we typically estimate a zIIP offload percentage of about 80% of the database workload processed by a CA Datacom/DB Release 15.1 MUF address space when zIIP processors are available. The zIIP offload for a given MUF can vary slightly depending on the workload that is processed (for example, day shift versus night shift, daily versus end of month).  


Another critical point to consider is that the zIIP offload percentage is directly affected by how well the MUF address space is tuned. MUF address spaces that utilize large buffer pools and memory resident data facility (MRDF) have reduced physical I/Os, which results in higher zIIP offload eligibility.  MUF address spaces with smaller buffer pools and limited MRDF get lessor zIIP offload eligibility.  


The following graphic depicts a simulated customer workload executed against a MUF running without SMPTASK (non-SMP), with SMPTASK in TCB mode only (SMP TCB), and with SMPTASK in SRB mode (SMP SRB/TCB).


Final note: We received recent examples of Release 15.1 customers exceeding 97% zIIP offloads for well-tuned MUF address spaces on a system with available zIIP processors. 

For additional details about the exploitation of zIIP processing in CA Datacom, watch for additional posts on:

  • Understanding CA Datacom® Symmetrical Multiprocessing and the IBM z Integrated Information Processor (zIIP)
  • Measuring CA Datacom® Symmetrical Multiprocessing and the IBM z Integrated Information Processor (zIIP)


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10-12-2020 12:52 PM

Datacom DBAs -- There will be two additional posts on understanding and measuring zIIP with CA Datacom that will be posted as follow-ups blogs.

Please elt me know if this information has been helpful and if you have any additional topics CA Datacom you would like to discuss.

Best regards,
Kevin Shuma