Hello, is it possible to use port 5 of the 53101M with an external PHY as a 5th port over RMII?
It's doable but please be noted as below items:
1. 53101M phy-less port Port5 does not support auto polling external phy device, it needs external CPU SW to implement the external phy polling then update external phy speed/duplex status to 53101M Port5 MAC through PortStateOverrideRegister(0x00: 0x5D) to make sync up between 53101M Port5 and external phy device.
Otherwise, only to force one speed/duplex on this external phy port and force 53101M Port5 speed/duplex via PortStateOverrideRegister through EEPROM.
2. It needs double check the external phy support the corresponding RMII interface.
Hi Ryan thank for the response. I should add more detail as follows:
Port 5 is actually connected to a WiFi bridge device via RMII, not a phy. At this point the 53101M is creating the 50MHz clock but I do not see any RMII traffic.
So there is no Phy. There is no processor, just eeprom. I tried to mirror port 1 traffic to port 5 with no success.
I believe I tried the override register to sync up. I will try again. Can u recommend a way to have the 53101M create traffic on port 5 for debug. I tried port mirroring but based on the MIB a status all the packets are dropped.
I was about the respin my pcb to replace 53101M but after receiving your support info I would like to try again to get port 5 running if it is doable via eeprom settings
Thank you for the help.
Get Outlook for Android
Please make sure your 53101 port5 frame forwarding be enabled and port5 be force link up.
Below is the EEPROM source file contain for the registers configure.
[EEPROM source .txt file]
//page offset reg size(byte) data
00 0B 1 06
00 0E 1 87
Hi Ryan, so I configured the switch as you suggested and verified the registers are programmed via SPI reads.
So far I do not see any traffic in the port 5 RMII interface. Is there a way to have the switch create traffic on the RMII interface without a MAC or PHY device on the bus. I suspect there could be a PCB manufacturing/assembly issue on the switch IS RMII interface. Can I have the switch generate traffic on the RMII interface that I can scope out?
If I do a ping on one of the other ports, is there a way to forward the traffic to port 5 (port mirror)?
1. There are strap pins MII2_MODE[1:0] in datasheet as below capture [Figure1] for your reference.
Could you double check your setting on your board?
To configure the RMII with external or internal clock that the MII2_TXC pin needs to corresponding as input or output 50MHz clock.
In addition, please double check the other strap pin /HW_FWDG_EN configure. It needs set /HW_FWDG = 0 to enable the frame forwarding.
2. It does not need to do the port mirror. You just to inject the broadcast packet into any one front port, then other ports including port5 will be received the broadcast packet.
Hello Ryan, I am setup for RMII with external clock. As I mentioned in the thread I do see the 53101M generating a 50MHz clock on the MII2_TXC pin. I also verified by the /HW_FWDG_EN state by reading a 0x06 from the Switch Mode register (Page:00: Addr 0x0B).
Here is a stupid question… how do I create a broadcast packet on one of the other ports? Can I just issue a ping to some address?
Below for your reference for broadcast packet creating:
1. use packet generator like IXIA/SmartBit to send out the broadcast packet into any of your 53101 front ports.
2. use any packet generator tool installed on PC and make the [DA=FF FF FF FF FF FF] broadcast packet to send out.
ps. the packet length is 64Bytes at least.
Hi Ryan, I just want to say thanks for the help…
I need your opinion… I think I may have a bad board (lifted pad under the 53101). What do you think?
When I look at the Port MIB registers corresponding to PORT 5 (Page 25), I see the following:
TXOctets (addr:0x00) incrementing
TXBroadcastPkts (addr:0x10) incrementing when I ping 192.168.1.255 (broadcast ping)
But I see no scope activity on the MII_2_TXEN,MII_2_TXD[1:0] pins.
What do you think?
Also, here are some of the registers I have read via the SPI interface..
PAGE ADRR VALUE
0 0x05 0x00
0 0x0B 0x06
0 0x0E 0x87
0 0x20 0x00
0 0x26 0x0000
0 0x5D 0x0B
1 0x00 0x28 01
1 0x04 0x04 04
1 0x06 0x00 00
1 0x08 0xFF 01
1 0x70 0x8E 13
1 0x72 0x00 00
1 0x74 0x00 00
2-1, please refer the following registers setting in EEPROM and ensure to implement it, set Reg(0x00: 0x5D) is to force link up the
53101M port5 at 100Mbps full duplex.
Previously I misunderstand you used the 53101M IMP port to connect with external phy, so I feedback you the EEPROM setting is for
IMP port force link up and not for port5. Sorry about this.
//page offset r eg size(byte) data
00 0B 1 06
00 5D 1 47
2-2, please double check again by setting Reg(0x00: 0x5D)=0x47.
If there is still problems please dump the register value you listed again, and I will double check it.